ICSSSTUB32872A - ICS

ICSSSTUB32872A 28-Bit Registered Buffer

This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUB32872A operates from a differential clock (CK and CK). Data .

Features

• 28-bit 1:1 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on RESET input
• 50% more dynamic driver strength than standard SSTU32864
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 96 Ball BGA (Top View) Functionality Truth Table In puts RESET H H H H H H H H H H H H L DCS0 L L L L L L H H H H H H X or floating DCS1 L L L H H H L L L H H H X or floating CK ↑ ↑ L or H ↑ ↑ L or H ↑ ↑ L or H ↑ ↑ L or H X.