ICSSSTUB32866B - ICS

ICSSSTUB32866B 25-Bit Configurable Registered Buffer

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32866B operates from a differential clock (CK.

Features

• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on CSR and RESET inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 Functionality Truth Table Inputs RST H H H H H H H H H H H H L DCS CSR Dn, DODT, DCKE ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ .