ICSSSTUA32S869B - ICS

ICSSSTUA32S869B 14-Bit Configurable Registered Buffer

The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized to drive the DDR2 DIMM load. They provide 50% more dynamic driver strength than the standard SST.

Features

• 14-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• 50% more dynamic driver strength than standard SSTU32864
• Supports LVCMOS switching levels on C1 and RESET# inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 150 BGA package
• Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 150 Ball BGA (Top View) Functionality Truth Table Inputs RESET# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or floating CSR# L L L H H H L L L H H H X or fl.