This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specific.
• 28-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs
and outputs
Applications
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
• Supports LVCMOS switching levels on CSGEN and
RESET inputs
• Ideal for DDR2 400, 533, and 667
• Low voltage operation: VDD = 1.7V to 1.9V
• Available in 176-ball LFBGA package
Block Diagram
M2
RESET
CLK CLK VREF
L1 M1
A5, AB5
DCKE0, DCKE1
D1, C1
2 2
F2, E2
D
2
QCKE0A, QCKE1A
CK R
Q
H8, F8
QCKE0B, QCKE1B QODT0A, QODT1A
DODT0, DODT1
N1, P1
.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ICSSSTUAF32868B |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
2 | ICSSSTUAF32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
3 | ICSSSTUAF32866B |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
4 | ICSSSTUAF32866C |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
5 | ICSSSTUAF32869A |
IDT |
14-BIT CONFIGURABLE REGISTERED BUFFER | |
6 | ICSSSTUA32S869B |
ICS |
14-Bit Configurable Registered Buffer | |
7 | ICSSSTUAH32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
8 | ICSSSTUAH32868A |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
9 | ICSSSTU32864 |
ICS |
25-Bit Configurable Registered Buffer | |
10 | ICSSSTU32866 |
Integrated Circuit System |
25-Bit Configurable Registered Buffer | |
11 | ICSSSTUB32864A |
ICS |
25-Bit Configurable Registered Buffer | |
12 | ICSSSTUB32866B |
ICS |
25-Bit Configurable Registered Buffer |