1:2 Register B (C0 = 1, C1 = 1) This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTU32864 operat.
• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on CSR# and RESET# inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package
Pin Configuration
1 A B C D E F G H J K L M N P R T 2 3 4 5 6
96 Ball BGA (Top View) Truth Table
I nputs RST# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or Floating CSR# L L L H H H L L L H H H X or Floating L or H X or Floating L or H X or Floating L or H L or H L or H L or H L or H L or H CK CK# Dn, DODT, DCK E L H X L H .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ICSSSTU32866 |
Integrated Circuit System |
25-Bit Configurable Registered Buffer | |
2 | ICSSSTUA32S869B |
ICS |
14-Bit Configurable Registered Buffer | |
3 | ICSSSTUAF32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
4 | ICSSSTUAF32866B |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
5 | ICSSSTUAF32866C |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
6 | ICSSSTUAF32868A |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
7 | ICSSSTUAF32868B |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
8 | ICSSSTUAF32869A |
IDT |
14-BIT CONFIGURABLE REGISTERED BUFFER | |
9 | ICSSSTUAH32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
10 | ICSSSTUAH32868A |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
11 | ICSSSTUB32864A |
ICS |
25-Bit Configurable Registered Buffer | |
12 | ICSSSTUB32866B |
ICS |
25-Bit Configurable Registered Buffer |