This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUAF32866C operates from a differential clock (C.
• 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check
functionality
• Supports SSTL_18 JEDEC specification on data inputs
and outputs
• Supports LVCMOS switching levels on C0, C1, and
RESET inputs
• Low voltage operation: VDD = 1.7V to 1.9V
• Drop-in replacement for ICSSSTUA32864
• Available in 96-ball BGA package
Applications
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
•
ICS98ULPA877A or IDTCSPUA877A Ideal for DDR2 400, 533, and 667
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
ICSSSTUAF32866C
7100/9
ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFF.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ICSSSTUAF32866B |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
2 | ICSSSTUAF32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
3 | ICSSSTUAF32868A |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
4 | ICSSSTUAF32868B |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
5 | ICSSSTUAF32869A |
IDT |
14-BIT CONFIGURABLE REGISTERED BUFFER | |
6 | ICSSSTUA32S869B |
ICS |
14-Bit Configurable Registered Buffer | |
7 | ICSSSTUAH32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER | |
8 | ICSSSTUAH32868A |
IDT |
28-BIT CONFIGURABLE REGISTERED BUFFER | |
9 | ICSSSTU32864 |
ICS |
25-Bit Configurable Registered Buffer | |
10 | ICSSSTU32866 |
Integrated Circuit System |
25-Bit Configurable Registered Buffer | |
11 | ICSSSTUB32864A |
ICS |
25-Bit Configurable Registered Buffer | |
12 | ICSSSTUB32866B |
ICS |
25-Bit Configurable Registered Buffer |