ICSSSTUB32864A - ICS

ICSSSTUB32864A 25-Bit Configurable Registered Buffer

1:2 Register B (C0 = 1, C1 = 1) This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32864A oper.

Features

• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on C0, C1 and RESET# inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUB32866
• Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 96 Ball BGA (Top View) Truth Table I nputs RST# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or Floating CSR# L L L H H H L L L H H H X or Floating L or H X or Floating L or H X or Floating L or .