T he HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is.
O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.2 Pinning diagram. HEF4518BP(N): HEF4518BD(F): HEF4518BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING CP0A, CP0B CP1A, CP1B MRA, MRB O0A to O3A O0B to O3B clock inputs (L to H triggered) clock inputs (H to L triggered) master reset inputs outputs outputs APPLICATION INFORMATION Some examples of applications fo.
The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has two clock inputs (CP0 and CP1 ), buffer.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4510B |
NXP |
BCD up/down counter | |
2 | HEF4511B |
NXP |
BCD to 7-segment latch/decoder/driver | |
3 | HEF4511B |
Philips |
BCD to 7-segment latch/decoder/driver | |
4 | HEF4512B |
NXP |
8-input multiplexer with 3-state output | |
5 | HEF4514B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
6 | HEF4515B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
7 | HEF4516B |
NXP |
Binary up/down counter | |
8 | HEF4517B |
NXP |
Dual 64-bit static shift register | |
9 | HEF4519B |
NXP |
Quadruple 2-input multiplexer | |
10 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
11 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory | |
12 | HEF4508B |
NXP |
Dual 4-bit latch |