The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outputs provided EO is LOW. Changing the ST input to the LOW state locks the HE.
dance OFF-state regardless of other input conditions. This allows the outputs to interface directly with bus orientated systems. When EO is LOW the contents of the latches are available at the outputs. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification Dual 4-bit latch HEF4508B MSI Fig.2 Pinning diagram. HEF4508BP(N): HEF4508BD(F): HEF4508BT(D): 24-lead DIL; plastic (SOT101-1) 24-lead DIL; ceramic (cerdip) (SOT94) 24-lead SO; plastic (SOT137-1) ( ): Package Designator North America PINN.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
2 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory | |
3 | HEF4510B |
NXP |
BCD up/down counter | |
4 | HEF4511B |
NXP |
BCD to 7-segment latch/decoder/driver | |
5 | HEF4511B |
Philips |
BCD to 7-segment latch/decoder/driver | |
6 | HEF4512B |
NXP |
8-input multiplexer with 3-state output | |
7 | HEF4514B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
8 | HEF4515B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
9 | HEF4516B |
NXP |
Binary up/down counter | |
10 | HEF4517B |
NXP |
Dual 64-bit static shift register | |
11 | HEF4518B |
NXP |
Dual BCD counter | |
12 | HEF4518B |
nexperia |
Dual BCD counter |