The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (D0 to D3), an active HIGH latch enable input (LE), an active LOW ripple blanking input (BL), an active LOW lamp test input (LT), and seven active HIGH NPN bipolar transistor segment outputs (Qa to Qg). When LE is LOW and BL is HIGH, the state of the segment outputs (Qa to Qg) .
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information All types operate from 40 C to +125 C.
Type number
Package
Name
Description
HEF4511BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4511BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version SOT38-4 SOT109-1
NXP Semiconductors
4. Functional diagram
HEF4511B
BCD to 7-segment latch/de.
The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (DA to DD), an active LOW latch enable .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4510B |
NXP |
BCD up/down counter | |
2 | HEF4512B |
NXP |
8-input multiplexer with 3-state output | |
3 | HEF4514B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
4 | HEF4515B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
5 | HEF4516B |
NXP |
Binary up/down counter | |
6 | HEF4517B |
NXP |
Dual 64-bit static shift register | |
7 | HEF4518B |
NXP |
Dual BCD counter | |
8 | HEF4518B |
nexperia |
Dual BCD counter | |
9 | HEF4519B |
NXP |
Quadruple 2-input multiplexer | |
10 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
11 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory | |
12 | HEF4508B |
NXP |
Dual 4-bit latch |