HEF4517B - NXP

HEF4517B Dual 64-bit static shift register

The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D input is entered into the first bit on the LOW to HIGH transition of the clock.

Features

4-bit shift register is divided into four 16-bit shift registers with D, O16, O32 and O48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category LSI See Family Specifications January 1995 2 Philips Semiconductors Product specification Dual 64-bit static shift register HEF4517B LSI Fig.2 Pinning diagram. HEF4517BP(N): HEF4517BD(F): HEF4517BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip).