The HEF4512B is an 8-input multiplexer with 8 binary inputs (I0 to I7), an enable input (E) and an output enable input (EO). One of eight binary inputs is selected by select inputs S0, S1 and S2, and is routed to the output O. A HIGH on EO causes O to assume a high impedance OFF-state, regardless of other input conditions. This allows the output HEF4512B MS.
ovide any logic functions of four variables. It cannot be used to multiplex analogue signals. Fig.2 Pinning diagram. HEF4512BP(N): HEF4512BD(F): HEF4512BT(D): Fig.1 Functional diagram. 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING S0, S1, S2 EO E I0 to I7 O select inputs output enable (active LOW) enable (active LOW) multiplexer inputs multiplexer output FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4510B |
NXP |
BCD up/down counter | |
2 | HEF4511B |
NXP |
BCD to 7-segment latch/decoder/driver | |
3 | HEF4511B |
Philips |
BCD to 7-segment latch/decoder/driver | |
4 | HEF4514B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
5 | HEF4515B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
6 | HEF4516B |
NXP |
Binary up/down counter | |
7 | HEF4517B |
NXP |
Dual 64-bit static shift register | |
8 | HEF4518B |
NXP |
Dual BCD counter | |
9 | HEF4518B |
nexperia |
Dual BCD counter | |
10 | HEF4519B |
NXP |
Quadruple 2-input multiplexer | |
11 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
12 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory |