HEF4505B - NXP

HEF4505B 64-bit/ 1-bit per word random access read/write memory

The HEF4505B is a 64-bit, 1-bit per word, fully decoded and completely static, random access memory. The memory is strobed for reading or writing only when the strobe input (ST), chip enable inputs (CE1 and CE2) are HIGH simultaneously. The output data is available at the data output (DOUT) only when the memory is strobed, the read/write input (R/W) is HIGH .

Features

led in the high-impedance OFF-state, when the memory is not strobed or R/W is LOW. R/W may remain HIGH during a read cycle or LOW during a write cycle. The output data has the same polarity as the input data. HEF4505BP(N): HEF4505BD(F): HEF4505B LSI Fig.1 Pinning diagram. 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) ( ): Package Designator North America PINNING A0 to A5 CE1, CE2 R/W ST DIN DOUT FUNCTION TABLE ST, CE1, CE2 R/W L H L H Note 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) Z = high-impedance OFF-state L L H H Z Z .