The HEF4515B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs (A0 to A3), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O0 to O15) are mutually exclusive active LOW. When EL is HIGH, the selected output is determined by the data on An. When EL goes LOW, the last data HEF4515B MSI present at An .
e input (E) does not affect the state of the latch. When the HEF4515B is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. Fig.1 Functional diagram. HEF4515BP(N): HEF4515BD(F): HEF4515BT(D): 24-lead DIL; plastic (SOT101-1) 24-lead DIL; ceramic (cerdip) (SOT94) 24-lead SO; plastic (SOT137-1) ( ): Package Designator North America Fig.2 Pinning diagram. APPLICATION INFORMATION Some examples of applications for the HEF4515B are: PINNING A0 to A3 E EL O0 to O15 address inputs enable input (active LOW) latch enable input outputs (active LOW) FAMILY DATA, IDD LIMIT.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4510B |
NXP |
BCD up/down counter | |
2 | HEF4511B |
NXP |
BCD to 7-segment latch/decoder/driver | |
3 | HEF4511B |
Philips |
BCD to 7-segment latch/decoder/driver | |
4 | HEF4512B |
NXP |
8-input multiplexer with 3-state output | |
5 | HEF4514B |
NXP |
1-of-16 decoder/demultiplexer with input latches | |
6 | HEF4516B |
NXP |
Binary up/down counter | |
7 | HEF4517B |
NXP |
Dual 64-bit static shift register | |
8 | HEF4518B |
NXP |
Dual BCD counter | |
9 | HEF4518B |
nexperia |
Dual BCD counter | |
10 | HEF4519B |
NXP |
Quadruple 2-input multiplexer | |
11 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
12 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory |