The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficien.
• Differential clock signals
• Supports SSTL_2 class II specifications on inputs and outputs
• Low-voltage operation - VDD = 2.3V to 2.7V
• Available in 114 ball BGA package.
Pin Configuration
1 A B C D E F G H J 2 3 4 5 6
Truth Table
RESET# L H H H
Notes: 1.
1
K L
Inputs CLK X or Floating ↑ ↑ L or H CLK# X or Floating ↓ ↓ L or H D X or Floating H L X
Q Outputs Q L H L Q0(2)
M N P R T U V W
114-Pin Ball BGA
H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care Output level before the indicated steady state input con.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ICSSSTV16857 |
Integrated Circuit Systems |
DDR 14-Bit Registered Buffer | |
2 | ICSSSTV16859 |
Integrated Circuit Systems |
DDR 13-Bit to 26-Bit Registered Buffer | |
3 | ICSSSTVA16857 |
Integrated Circuit Systems |
DDR 14-Bit Registered Buffer | |
4 | ICSSSTVA16859B |
Integrated Circuit Systems |
DDR 13-Bit to 26-Bit Registered Buffer | |
5 | ICSSSTVA16859C |
Renesas |
DDR 13-Bit to 26-Bit Registered Buffer | |
6 | ICSSSTVA16859C |
IDT |
DDR 13-Bit to 26-Bit Registered Buffer | |
7 | ICSSSTVF16857 |
Renesas |
DDR 14-Bit Registered Buffer | |
8 | ICSSSTVF16859 |
Integrated Circuit Systems |
DDR 13-Bit to 26-Bit Registered Buffer | |
9 | ICSSSTU32864 |
ICS |
25-Bit Configurable Registered Buffer | |
10 | ICSSSTU32866 |
Integrated Circuit System |
25-Bit Configurable Registered Buffer | |
11 | ICSSSTUA32S869B |
ICS |
14-Bit Configurable Registered Buffer | |
12 | ICSSSTUAF32865A |
IDT |
25-BIT CONFIGURABLE REGISTERED BUFFER |