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ICSSSTVA16859C - Renesas

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ICSSSTVA16859C DDR 13-Bit to 26-Bit Registered Buffer

The 13-bit-to-26-bit ICSSSTVA16859C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain suffici.

Features


• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class I specifications on outputs
• Low-voltage operation - VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF packages
• Exceeds ICSSSTVN16859 performance Truth Table1 RESET# L H H H Notes: Inputs CLK CLK# X or X or Floating Floating ↑↓ ↑↓ L or H L or H Q Outputs DQ X or Floating L HH LL X Q0(2) 1. H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care 2. Output level before the indicated steady state input conditions were.

The same part from a different manufacturer

Datasheet ICSSSTVA16859C - IDT ICSSSTVA16859C

ICSSSTVA16859C DDR 13-Bit to 26-Bit Registered Buffer Recommended Applications: • DDR Memory Modules: - DDRI (PC1600, .

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