ICSSSTV32852 |
Part Number | ICSSSTV32852 |
Manufacturer | Integrated Circuit Systems |
Description | The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/ O levels, except for the LVCMOS RESET# input. Data flow from D to Q is controlled by t... |
Features |
• Differential clock signals • Supports SSTL_2 class II specifications on inputs and outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 114 ball BGA package. Pin Configuration 1 A B C D E F G H J 2 3 4 5 6 Truth Table RESET# L H H H Notes: 1. 1 K L Inputs CLK X or Floating ↑ ↑ L or H CLK# X or Floating ↓ ↓ L or H D X or Floating H L X Q Outputs Q L H L Q0(2) M N P R T U V W 114-Pin Ball BGA H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care Output level before the indicated steady state input con... |
Document |
ICSSSTV32852 Data Sheet
PDF 146.82KB |
Distributor | Stock | Price | Buy |
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No. | Partie # | Fabricant | Description | Fiche Technique |
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1 | ICSSSTV16857 |
Integrated Circuit Systems |
DDR 14-Bit Registered Buffer | |
2 | ICSSSTV16859 |
Integrated Circuit Systems |
DDR 13-Bit to 26-Bit Registered Buffer | |
3 | ICSSSTVA16857 |
Integrated Circuit Systems |
DDR 14-Bit Registered Buffer | |
4 | ICSSSTVA16859B |
Integrated Circuit Systems |
DDR 13-Bit to 26-Bit Registered Buffer | |
5 | ICSSSTVA16859C |
Renesas |
DDR 13-Bit to 26-Bit Registered Buffer |