The HEF4555B is a dual 1-of-4 decoder/demultiplexer. Each has two address inputs (A0 and A1), an active LOW enable input (E) and four mutually exclusive outputs which are active HIGH (O0 to O3). When used as a decoder, E when HIGH, forces O0 to O3 LOW. When used as a demultiplexer, the appropriate output is selected by the information on A0 and A1 with E as .
(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING E A0 and A1 O0 to O3 enable inputs (active LOW) address inputs outputs (active HIGH) FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Dual 1-of-4 decoder/demultiplexer Product specification HEF4555B MSI Fig.3 Logic diagram (one decoder/multiplexer). TRUTH TABLE INPUTS OUTPUTS E A0 LL LH LL LH HX A1 L L H H X O0 O1 HL LH LL LL LL O2 L L H L L Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = stat.
The HEF4555B contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (nA0 and nA1, an active LOW enable.
The HEF4555B contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (nA0 and nA1, an active LOW enabl.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4555B-Q100 |
nexperia |
1-of-4 decoder/demultiplexer | |
2 | HEF4556B |
NXP |
Dual 1-of-4 decoder/demultiplexer | |
3 | HEF4557B |
NXP |
1-to-64 bit variable length shift register | |
4 | HEF4557B |
Philips |
1-to-64 bit variable length shift register | |
5 | HEF4557B |
nexperia |
1-to-64 bit variable length shift register | |
6 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
7 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory | |
8 | HEF4508B |
NXP |
Dual 4-bit latch | |
9 | HEF4510B |
NXP |
BCD up/down counter | |
10 | HEF4511B |
NXP |
BCD to 7-segment latch/decoder/driver | |
11 | HEF4511B |
Philips |
BCD to 7-segment latch/decoder/driver | |
12 | HEF4512B |
NXP |
8-input multiplexer with 3-state output |