The HEF4555B-Q100 contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (nA0 and nA1, an active LOW enable input (nE) and four mutually exclusive outputs which are active HIGH (nY0 to nY3). When used as a decoder, nE when HIGH, forces nY0 to nY3 LOW. When used as a demultiplexer, the appropriate output is selected by the information on nA0.
• Automotive product qualification in accordance with AEC-Q100 (Grade 3)
• Specified from -40 °C to +85 °C
• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
• Complies with JEDEC standard JESD 13-B
3. Applications
• Code conversion
• Address decoding
• Demultiplexing: when using the .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF4555B |
NXP |
1-of-4 decoder/demultiplexer | |
2 | HEF4555B |
Philips |
Dual 1-of-4 decoder/demultiplexer | |
3 | HEF4555B |
nexperia |
1-of-4 decoder/demultiplexer | |
4 | HEF4556B |
NXP |
Dual 1-of-4 decoder/demultiplexer | |
5 | HEF4557B |
NXP |
1-to-64 bit variable length shift register | |
6 | HEF4557B |
Philips |
1-to-64 bit variable length shift register | |
7 | HEF4557B |
nexperia |
1-to-64 bit variable length shift register | |
8 | HEF4502B |
NXP |
Strobed hex inverter/buffer | |
9 | HEF4505B |
NXP |
64-bit/ 1-bit per word random access read/write memory | |
10 | HEF4508B |
NXP |
Dual 4-bit latch | |
11 | HEF4510B |
NXP |
BCD up/down counter | |
12 | HEF4511B |
NXP |
BCD to 7-segment latch/decoder/driver |