The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capaci.
ysical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74132 S-52019⎯Rev. A, 03-Oct-05 www.vishay.com 1 SPICE Device Model Si5941DU Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data Measured Data Unit VGS(th) ID(on) VDS = V.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SI5943DU |
Vishay Siliconix |
Dual P-Channel 12-V (D-S) MOSFET | |
2 | SI5944DU |
Vishay Siliconix |
Dual N-Channel MOSFET | |
3 | SI5945DU |
Vishay Siliconix |
Dual P-Channel 20-V (D-S) MOSFET | |
4 | SI5948DU |
Vishay |
MOSFET | |
5 | SI590 |
Silicon Laboratories |
CRYSTAL OSCILLATOR | |
6 | SI5902BDC |
Vishay Siliconix |
Dual N-Channel MOSFET | |
7 | SI5902DC |
Vishay Siliconix |
Dual N-Channel MOSFET | |
8 | SI5903DC |
Vishay Siliconix |
Dual P-Channel MOSFET | |
9 | SI5904DC |
Vishay Siliconix |
Dual N-Channel MOSFET | |
10 | SI5905BDC |
Vishay Siliconix |
Dual P-Channel MOSFET | |
11 | SI5905DC |
Vishay Siliconix |
Dual P-Channel MOSFET | |
12 | SI5906DU |
Vishay Siliconix |
Dual N-Channel MOSFET |