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The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AV dd to ground. BLOCK DIAGRAM Programmable Skew Channel -.
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
• Distributes one clock Input to one bank of ten differential outputs.
• Track spread spectrum clocking for EMI reduction.
• Programmable delay between CLK_INT and CLK[T/C] from
–0.8ns to +3.1ns by programming www.DataSheet4U.com CLKINT and FBOUT skew channel, or from
–1.1ns to +3.5ns if additional DDR skew channels are enabled.
• Four independent programmable DDR skew channels from
–0.3ns to +0.4ns with step size ± 100ps.
• Support 2-wire I2C serial bus interface.
• 2.5V Operating Voltage.
• Available in 48-.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | PLL102-10 |
PhaseLink Corporation |
Low Skew Output Buffer |
|
| 2 | PLL102-109 |
PhaseLink Corporation |
Programmable DDR Zero Delay Clock Driver |
|
| 3 | PLL102-15 |
PhaseLink Corporation |
Low Skew Output Buffer |
|
| 4 | PLL102-03 |
PhaseLink Corporation |
Low Skew Output Buffer |
|
| 5 | PLL102-04 |
PhaseLink Corporation |
Low Skew Output Buffer |
|
| 6 | PLL102-05 |
PhaseLink Corporation |
Low Skew Output Buffer |
|
| 7 | PLL1000A |
Z-Communications |
PHASE LOCKED LOOP |
|
| 8 | PLL103-01 |
PhaseLink Corporation |
Low Skew Buffer |
|
| 9 | PLL103-02 |
PhaseLink Corporation |
DDR SDRAM Buffer |
|
| 10 | PLL103-03 |
PhaseLink Corporation |
DDR SDRAM Buffer |
|
| 11 | PLL103-04 |
PhaseLink Corporation |
1-to-4 Clock Distribution Buffer |
|
| 12 | PLL103-05 |
PhaseLink Corporation |
1-to-5 Clock Distribution Buffer |
|