P7NB60 - ST Microelectronics

P7NB60 STP7NB60FP

Using the latest high voltage MESH OVERLAY™ process, SGS-Thomson has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and s.

Features

Tj March 1998 Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at Tc = 25 o C Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) Total Dissipation at T c = 25 C Derating Factor Peak Diode Recovery voltage slope Insulation W ithstand Voltage (DC) Storage Temperature Max. O perating Junction Temperature o TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value ST P7NB60 STP7NB60FP 600 600 ± 30 7.2 4.5 28.8 125 1.0 4.5  -65 to 150 150 (1) ISD ≤ 7A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Uni t V V V 4..