P7NB80FP - ST Microelectronics

P7NB80FP STP7NB80

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

• ) P tot dv/dt( 1 ) V ISO Ts tg Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (RGS = 20 kΩ ) Gate-source Voltage Drain Current (continuous) at Tc = 25 o C Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) T otal Dissipation at Tc = 25 o C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction T emperature TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value STP7NB80 STP7NB80F P 800 800 ± 30 6.5 4.1 26 135 1.08 4.5 --65 to 150 150 ( 1) ISD ≤ 6.5A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJ.