P4NB80FP - STMicroelectronics

P4NB80FP STP4NB80FP

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

DS V DGR V GS ID ID IDM (
• ) P tot dv/dt(1 ) V ISO T stg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at T c = 25 o C Drain Current (continuous) at T c = 100 C Drain Current (pulsed) Total Dissipation at T c = 25 o C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature o Value STP4NB80 STP4NB80FP 800 800 ± 30 4 2.4 16 100 0.8 4.5  -65 to 150 150 (1) ISD ≤4 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Unit V V V A A A .