P4NB10 - ST Microelectronics

P4NB10 STP4NB10

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

DM (
• ) P tot dv/dt( 1) V ISO Ts tg Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 kΩ ) Gate-source Voltage Drain Current (continuous) at Tc = 25 o C Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) T otal Dissipation at Tc = 25 o C Derating F actor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction T emperature TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value STP4NB100 ST P4NB100F P 1000 1000 ± 30 3.8 2.4 15.2 125 1 4  -65 to 150 150 ( 1) ISD ≤ 3.8A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS.