MT5C1001 1M x 1 SRAM Datasheet

MT5C1001 1M x 1 SRAM

The MT5C1001 employs low power, high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. For ﬂexibility in high-speed memory applications, Micross offers chip enable (CE) and output enable (OE) capability. These e.

Features

• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE and OE options.
• All inputs and outputs are TTL compatible
• Three-state output OPTIONS
• Timing 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access MARKING -20 -25 -35 -45 -55
* -70
*
• Package(s) Ceramic DIP (400 mil) Ceramic LCC Ceramic Flatpack Ceramic SOJ C No. 109 EC No. 207 F No. 303 DCJ No. 501
• Operating Temperature Ranges Industrial (-40oC to +85oC) IT Military (-55oC to +125oC) XT
• 2V data retent.

The same part from a different manufacturer

MT5C1001 - ASI

The MT5C1001 employs low power, high-performance silicon-gate CMOS technology. Static design eliminates the need for ext.

MT5C1001 - Micron

The MT5C1001 is organized as a 1,048,576 x 1 SRAM using a four-transistor m.

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MT5C1001 - Micross