MT5C1008 - ASI

MT5C1008 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. For design flexibility in high-speed memory applications, this device offers dual chip enables (CE1, CE2) and output enable (OE). These control pins can place the outputs in High-Z.

Features

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• High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS process Single +5V (+10%) Power Supply Easy memory expansion with CE1, CE2, and OE options.
• All inputs and outputs are TTL compatible 32-Pin LCC (ECA) 4 3 2 1 32 31 30 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE DQ8 DQ7 DQ6 DQ5 DQ4 OPTIONS
• Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns.