The HEF40195B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a buffered inverted output from the last bit position (O3) and a.
195B MSI input. When PE is LOW, data are loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. When PE is HIGH, data are shifted into the first register position from J and K and all the data in the register are shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J is HIGH and K is LOW, the first stage is in the toggle mode. When J is LOW and K is HIGH, the first stage is in the hold mode. A LOW on MR resets all four bit positions (O0 to O3 = LOW, O3 = HIGH) independent of all other input conditi.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF40192B |
NXP |
4-bit up/down decade counter | |
2 | HEF40193B |
NXP |
4-bit up/down binary counter | |
3 | HEF40194B |
NXP |
4-bit bidirectional universal shift register | |
4 | HEF4019B |
NXP |
Quadruple 2-input multiplexer | |
5 | HEF40106B |
NXP |
Hex inverting Schmitt trigger | |
6 | HEF40106B |
Philips |
Hex inverting Schmitt trigger | |
7 | HEF40106B |
nexperia |
Hex inverting Schmitt trigger | |
8 | HEF40106B-Q100 |
nexperia |
Hex inverting Schmitt trigger | |
9 | HEF4011B |
NXP |
Quadruple 2-input NAND gate | |
10 | HEF4011B |
Philips |
Quadruple 2-input NAND gate | |
11 | HEF4011B |
nexperia |
Quad 2-input NAND gate | |
12 | HEF4011B-Q100 |
nexperia |
Quad 2-input NAND gate |