HEF40192B - NXP

HEF40192B 4-bit up/down decade counter

The HEF40192B is a 4-bit synchronous up/down decade counter. The counter has a count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel load input (PL), four parallel data inputs (P0 to P3), an asynchronous master reset input (MR), four counter outputs (O0 to O3), an active LOW terminal count-up (carry) output (TCU) and an active .

Features

ly. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of ‘9’, the next HIGH to LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on P0 to P3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop. Fig.2 Pinning diagram. HEF40192BP(N): 16-lead DIL; plastic (SOT38-1) Fi.