HEF4019B - NXP

HEF4019B Quadruple 2-input multiplexer

The HEF4019B provides four multiplexing circuits with common select inputs (SA, SB); each circuit contains two inputs (An, Bn) and one output (On). It may be used to select four bits of information from one of two sources. HEF4019B MSI The A inputs are selected when SA is HIGH, the B inputs when SB is HIGH. When SA and SB are HIGH, output (On) is the logica.

Features

T38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING SA, SB A0 to A3 FAMILY DATA, IDD LIMITS category MSI See Family Specifications B0 to B3 O0 to O3 select inputs (active HIGH) multiplexer inputs multiplexer inputs multiplexer outputs Fig.2 Pinning diagram. January 1995 2 Philips Semiconductors Product specification Quadruple 2-input multiplexer HEF4019B MSI Fig.3 Logic diagram. TRUTH TABLE SELECT SA L H H L L H H H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = sta.