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HD74LS10 Triple 3-Input Positive NAND Gates Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS10P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS10FPEL SOP-14 pin (JEITA) PRSP0014DF-B FP (FP-14DAV) HD74LS10RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sa.
• Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74LS10P
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
HD74LS10FPEL SOP-14 pin (JEITA)
PRSP0014DF-B
FP
(FP-14DAV)
HD74LS10RPEL
SOP-14 pin (JEDEC)
PRSP0014DE-A (FP-14DNV)
RP
Note: Please consult the sales office for the above package availability.
Pin Arrangement
REJ03D0396
–0200 Rev.2.00
Feb.18.2005
Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel)
1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7
14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A 8 3Y
(Top view)
Rev.2.00, Feb.18.2005, page.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | HD74LS10 |
Hitachi Semiconductor |
Triple 3-input Positive NAND Gates |
|
| 2 | HD74LS10 |
Renesas |
Triple 3-Input Positive NAND Gates |
|
| 3 | HD74LS107A |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 4 | HD74LS107A |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 5 | HD74LS107AP |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 6 | HD74LS109 |
Hitachi Semiconductor |
Dual J-K Positive-edge-triggered Flip-Flops |
|
| 7 | HD74LS109A |
Hitachi Semiconductor |
Dual J-K Positive-edge-triggered Flip-Flops |
|
| 8 | HD74LS11 |
Hitachi Semiconductor |
Triple 3-input Positive AND Gates |
|
| 9 | HD74LS11 |
Renesas |
Triple 3-input Positive AND Gates |
|
| 10 | HD74LS112 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 11 | HD74LS112 |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 12 | HD74LS112P |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops |
|