Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.4.
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HD74LS10 Triple 3-Input Positive NAND Gates Features • Ordering Information Part Name Package Type Package Code (Pre.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74LS107A |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops | |
2 | HD74LS107A |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
3 | HD74LS107AP |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
4 | HD74LS109 |
Hitachi Semiconductor |
Dual J-K Positive-edge-triggered Flip-Flops | |
5 | HD74LS109A |
Hitachi Semiconductor |
Dual J-K Positive-edge-triggered Flip-Flops | |
6 | HD74LS10P |
Renesas |
Triple 3-Input Positive NAND Gates | |
7 | HD74LS11 |
Hitachi Semiconductor |
Triple 3-input Positive AND Gates | |
8 | HD74LS11 |
Renesas |
Triple 3-input Positive AND Gates | |
9 | HD74LS112 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops | |
10 | HD74LS112 |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
11 | HD74LS112P |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
12 | HD74LS113 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops |