HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops (with Clear) REJ03D0425–0300 Rev.3.00 Jul.13.2005 Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS107AP DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS107AFPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP Note: Please consult the sa.
• Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74LS107AP
DILP-14 pin
PRDP0014AB-B (DP-14AV)
P
HD74LS107AFPEL SOP-14 pin (JEITA)
PRSP0014DF-B (FP-14DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantity) —
EL (2,000 pcs/reel)
Pin Arrangement
1J 1 1Q 2 1Q 3 1K 4 2Q 5 2Q 6 GND 7
CLR J Q CK QK
QK Q CK
CLR J
(Top view)
14 VCC 13 1CLR 12 1CK 11 2K 10 2CLR 9 2CK 8 2J
Function Table
Inputs
Outputs
Clear
Clock
J
K
QQ
LXXX LH
H ↓ L L QO QO H↓ H L HL
H↓ LHLH
H↓HH
Toggl.
Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74LS107AP |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
2 | HD74LS10 |
Hitachi Semiconductor |
Triple 3-input Positive NAND Gates | |
3 | HD74LS10 |
Renesas |
Triple 3-Input Positive NAND Gates | |
4 | HD74LS109 |
Hitachi Semiconductor |
Dual J-K Positive-edge-triggered Flip-Flops | |
5 | HD74LS109A |
Hitachi Semiconductor |
Dual J-K Positive-edge-triggered Flip-Flops | |
6 | HD74LS10P |
Renesas |
Triple 3-Input Positive NAND Gates | |
7 | HD74LS11 |
Hitachi Semiconductor |
Triple 3-input Positive AND Gates | |
8 | HD74LS11 |
Renesas |
Triple 3-input Positive AND Gates | |
9 | HD74LS112 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops | |
10 | HD74LS112 |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
11 | HD74LS112P |
Renesas |
Dual J-K Negative-edge-triggered Flip-Flops | |
12 | HD74LS113 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops |