EM638325 - Etron Technology

EM638325 2M x 32 Synchronous DRAM

2Mega x 32 SDRAM EM638325 Table 1. Pin Details of EM638325 Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signa.

Features

Clock rate: 200/183/166/143/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (512K x 32bit x 4bank) Programmable Mode - CAS# Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write
• Burst stop function
• Individual byte controlled by DQM0-3
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm pin pitch Lead Free Package available
•
•
•
•
•
• EM638325 2M x 32 Synchronous DRAM.