EM637327 - Etron Technology Inc.

EM637327 1Mega x 32 SGRAM

1Mega x 32 SGRAM EM637327 Table 1. Pin Details of EM637327 Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signa.

Features

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• EM637327 1Mega x 32 SGRAM Preliminary (08/99) Pin Assignment (Top View) DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC V DD DQ0 DQ1 VSSQ DQ2
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• Fast access time from clock: 4.5/5.5/5.5/6 ns Fast clock rate: 200/166/143/125 MHz Fully synchronous operation Internal pipelined architecture Dual internal banks (512K x 32bit x 2bank) Programmable Mode - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write - Load Color or Mask register Burst stop function Individual byte controlled by .