BSP120 - NXP

BSP120 N-channel enhancement mode vertical D-MOS transistor

N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use as a line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. FEATURES • Direct interface to C-MOS, TTL, etc. • High-speed switching • No secondary breakdown QUICK REFERENCE DATA Drain-source voltag.

Features

• Direct interface to C-MOS, TTL, etc.
• High-speed switching
• No secondary breakdown QUICK REFERENCE DATA Drain-source voltage Drain-current (DC) Drain-source ON-resistance ID = 250 mA; VGS = 10 V Gate threshold voltage PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain Marking code BSP120 PIN CONFIGURATION RDS(on) VGS(th) typ. max. max. VDS ID max. max. BSP120 200 V 250 mA 7 Ω 12 Ω 2.8 V handbook, halfpage 4 d g 1 Top view 2 3 MAM054 s Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS.