The TC58DVG02A1 is a single 3.3 V 1-Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Eras.
• Organization Memory cell allay 528 × 256K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Multi Block Program, Multi Block Erase Mode control Serial input/output Command control
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• Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array to register 25 µs max Serial Read Cycle 50 ns min Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 50 µA max. Package TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
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No. | Partie # | Fabricant | Description | Fiche Technique |
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1 | TC58DVG02A1FI0 |
Toshiba |
1 Gbit (128M x *8its) CMOS NAND EPROM | |
2 | TC58DVG02A1FT00 |
Toshiba Semiconductor |
MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS | |
3 | TC58DVG3S0ETA00 |
Toshiba |
8-GBIT (1G x 8-BIT) CMOS NAND E2PROM | |
4 | TC58DVM72A1FT00 |
Toshiba |
(TC58DxM72) 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM | |
5 | TC58DVM72F1FT00 |
Toshiba |
(TC58DxM72) 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM | |
6 | TC58DVM82A1FT00 |
Toshiba Semiconductor |
256-MBIT (32M x 8 BITS) CMOS NAND E2PROM | |
7 | TC58DVM92A1FT0 |
Toshiba |
512M-Bit CMOS NAND EPROM | |
8 | TC58DVM92A1FT00 |
Toshiba |
512M-Bit CMOS NAND EPROM | |
9 | TC58DVM92A5TA00 |
Toshiba |
512M-BIT (64M x 8 BITS) CMOS NAND E2PROM | |
10 | TC58DVM92A5TAI0 |
Toshiba |
512M-BIT (64M x 8 BITS) CMOS NAND E2PROM | |
11 | TC58DAM72A1FT00 |
Toshiba |
(TC58DxM72) 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM | |
12 | TC58DAM72F1FT00 |
Toshiba |
(TC58DxM72) 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM |