STP1030 - SPARC

STP1030 High-Performance 64-Bit RISC Processor

SPARC Technology Business Preliminary STP1030 May 1995 DATA SHEET UltraSPARC-I High-Performance 64-Bit RISC Processor INTRODUCTION The STP1030, UltraSPARC-I, is a high-performance, highly-integrated superscalar processor implementing the SPARC V9 64-bit RISC architecture. The STP1030 is capable of sustaining the execution of up to four instructions per c.

Features

• SPARC V9 Architecture Compliant
• Binary Compatible with all SPARC Application code
• VISual (Multimedia Capable) Instruction Set
• Multi-Processing Support - Glueless 4-processor connection with minimum latency - Snooping or Directory Based Protocol Support
• 4-way SuperScalar Design with 9 execution units - 4 Integer Execution Units - 3 Floating-point Execution Units - 2 Graphics Execution Units
• Selectable Little or Big Endian Byte Ordering
• 64-Bit Address Pointers
• 16KByte Non-blocking Data Cache
• 16KByte Instruction Cache - In-Cache 2-bit Branch Prediction - Single Cycle Branch Fol.