SSTUM32865 - NXP

SSTUM32865 1.8 V 28-bit 1 : 2 registered buffer

The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board.

Features

over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. The SSTUM32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, whic.