The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUA32864 operates from a different.
s s s s s s s s s s s s Configurable register supporting DDR2 Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Exceeds SSTUA32864 JEDEC specification speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Differential clock (CK a.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SSTUA32866 |
NXP |
configurable registered buffer | |
2 | SSTU32864 |
NXP |
1.8V confgurable registered buffer | |
3 | SSTU32865 |
NXP |
28-bit 1:2 registered buffer | |
4 | SSTU32866 |
NXP |
1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer | |
5 | SSTUB32866 |
NXP |
configurable registered buffer | |
6 | SSTUB32868 |
NXP |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity | |
7 | SSTUH32864 |
NXP |
1.8 V high output drive configurable registered buffer | |
8 | SSTUH32865 |
NXP |
1.8V 28-bit high output drive 1:2 registered buffer | |
9 | SSTUH32866 |
NXP |
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer | |
10 | SSTUM32865 |
NXP |
1.8 V 28-bit 1 : 2 registered buffer | |
11 | SST108 |
Calogic |
N-Channel JFET Switch | |
12 | SST108 |
Micross |
Switching |