The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby .
s 28-bit data register supporting DDR2 s Higher output drive strength version of SSTU32865 optimized for high-capacitive load nets s Fully compliant to JEDEC standard JESD82-9 s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTU32864 or 2 × SSTU32866) s Parity checking function across 22 input data bits s Parity out signal s Controlled output impedance drivers enable optimal signal integrity and speed s Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switching.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SSTUH32864 |
NXP |
1.8 V high output drive configurable registered buffer | |
2 | SSTUH32866 |
NXP |
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer | |
3 | SSTU32864 |
NXP |
1.8V confgurable registered buffer | |
4 | SSTU32865 |
NXP |
28-bit 1:2 registered buffer | |
5 | SSTU32866 |
NXP |
1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer | |
6 | SSTUA32864 |
NXP |
configurable registered buffer | |
7 | SSTUA32866 |
NXP |
configurable registered buffer | |
8 | SSTUB32866 |
NXP |
configurable registered buffer | |
9 | SSTUB32868 |
NXP |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity | |
10 | SSTUM32865 |
NXP |
1.8 V 28-bit 1 : 2 registered buffer | |
11 | SST108 |
Calogic |
N-Channel JFET Switch | |
12 | SST108 |
Micross |
Switching |