The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter con.
s s s s s s s s s s s s s s Configurable register supporting DDR2 up to 667 MT/s Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Checks parity on the DIMM-.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SSTUA32864 |
NXP |
configurable registered buffer | |
2 | SSTU32864 |
NXP |
1.8V confgurable registered buffer | |
3 | SSTU32865 |
NXP |
28-bit 1:2 registered buffer | |
4 | SSTU32866 |
NXP |
1.8V 25-bit 1:1 or 14-bit 1:2 confgurable registered buffer | |
5 | SSTUB32866 |
NXP |
configurable registered buffer | |
6 | SSTUB32868 |
NXP |
1.8 V 28-bit 1 : 2 configurable registered buffer with parity | |
7 | SSTUH32864 |
NXP |
1.8 V high output drive configurable registered buffer | |
8 | SSTUH32865 |
NXP |
1.8V 28-bit high output drive 1:2 registered buffer | |
9 | SSTUH32866 |
NXP |
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer | |
10 | SSTUM32865 |
NXP |
1.8 V 28-bit 1 : 2 registered buffer | |
11 | SST108 |
Calogic |
N-Channel JFET Switch | |
12 | SST108 |
Micross |
Switching |