SSTUB32866 - NXP

SSTUB32866 configurable registered buffer

The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUB32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter con.

Features

I I I I I I I I I I I I I I Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Meets or exceeds SSTUB32866 JEDEC standard speed performance Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Checks parity on the DIMM-independent data inputs Partial parity output and input.