P3NB80 - ST Microelectronics

P3NB80 STP3NB80

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

ID I DM (
• ) P tot dv/dt( 1 ) VISO Tstg Tj Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at T c = 25 o C Drain Current (pulsed) Total Dissipation at T c = 25 o C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature Drain Current (continuous) at T c = 100 o C m o .c U 4 t e e h S a t a .D w w w 3 1 2 3 2 1 TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Parameter Value 800 Unit V V V A A A STP3NB80 STP3NB80FP 800 ± 30 2.6 (
•).