P11NB40FP - STMicroelectronics

P11NB40FP STP11NB40FP

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

t dv /dt ( 1 ) V ISO Tst g Tj Parameter Dr ai n-sour ce Voltage (V GS =0 ) Drain- gate Volt age (R GS =2 0 k Ω ) G ate-so urc e Vo ltage Dra in Curre nt (co ntinuous) at Tc =2 5 C Dra in Curre nt (co ntinuous) at Tc =1 00 oC6 Drain Curren t (pu lsed) T ota l Dissipation at Tc =2 5 o C Dera ting Factor Peak Dio de Rec overy volt age slop e Insu lation W ithst and Voltage (DC) Stor age Tempe rat ure Max. Operating Junc tion Tempe rature o TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value ST P11NB4 0 STP11NB 40F P 400 40 0 ± 30 10. 7 .7 42. 8 125 1.0 4.5  -65 to 150 150 ( 1)I SD ≤ 10.7A, di/.