MTP60N05HDL - Motorola

MTP60N05HDL TMOS POWER FET

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP60N05HDL/D Product Preview HDTMOS E-FET.™ Power Field Effect Transistor N–Channel Enhancement–Mode Silicon Gate This advanced high–cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to.

Features

ES 50 VOLTS RDS(on) = 0.014 OHM ™ D G CASE 221A
  –06, Style 5 TO
  –220AB S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain
  –to
  –Source Voltage Drain
  –to
  –Gate Voltage (RGS = 1.0 MΩ) Gate
  –to
  –Source Voltage — Continuous — Non
  –Repetitive (tp ≤ 10 ms) Drain Current — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain
  –to
  –Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω) Thermal Resistance — Junction to Case — Junct.