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PIN CLK EN MR VBB Q0, Q1 Q2, Q3 DIVSEL FUNCTION Diff Clock Inputs Sync Enable Master Reset Reference Output Diff ÷2/4 Outputs Diff ÷4/6 Outputs Frequency Select Input FUNCTION TABLE CLK Z ZZ X EN L H X MR L L H FUNCTION Divide Hold Q0–3 Reset Q0–3 • • • • • • 50ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization 75kΩ Inter.
single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all .
MC100LVEL39 - ON Semiconductor
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applica.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MC100LVEL30 |
Motorola |
Triple D Flip-Flop |
|
| 2 | MC100LVEL30 |
ON Semiconductor |
Triple D Flip-Flop |
|
| 3 | MC100LVEL31 |
Motorola |
D Flip-Flop |
|
| 4 | MC100LVEL31 |
ON Semiconductor |
3.3V ECL D Flip?Flop |
|
| 5 | MC100LVEL32 |
Motorola |
Divider |
|
| 6 | MC100LVEL32 |
ON Semiconductor |
2 Divider |
|
| 7 | MC100LVEL33 |
Motorola |
Divider |
|
| 8 | MC100LVEL33 |
ON Semiconductor |
Divider |
|
| 9 | MC100LVEL34 |
ON Semiconductor |
Clock Generation Chip |
|
| 10 | MC100LVEL37 |
Motorola |
ECL/PECL Clock Fanout Buffer |
|
| 11 | MC100LVEL37 |
ON Semiconductor |
Clock Fanout Buffer |
|
| 12 | MC100LVEL38 |
ON Semiconductor |
Clock Generation Chip |
|