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The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple LVEL32’s in a system. The VBB pin, an internal.
• 510 ps Propagation Delay
• 2.6 GHz Typical Maximum Frequency
• ESD Protection:
♦ > 4 KV Human Body Model ♦ > 200 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity:
♦ Level 1 for SOIC−8 ♦ Level 3 for TSSOP−8 ♦ Level 1 for DFN−8 ♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
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MC100LVEL32 - Motorola
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview ÷2 Divider The MC100LVEL32 is an integrated ÷2 divider. The diffe.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MC100LVEL30 |
Motorola |
Triple D Flip-Flop |
|
| 2 | MC100LVEL30 |
ON Semiconductor |
Triple D Flip-Flop |
|
| 3 | MC100LVEL31 |
Motorola |
D Flip-Flop |
|
| 4 | MC100LVEL31 |
ON Semiconductor |
3.3V ECL D Flip?Flop |
|
| 5 | MC100LVEL33 |
Motorola |
Divider |
|
| 6 | MC100LVEL33 |
ON Semiconductor |
Divider |
|
| 7 | MC100LVEL34 |
ON Semiconductor |
Clock Generation Chip |
|
| 8 | MC100LVEL37 |
Motorola |
ECL/PECL Clock Fanout Buffer |
|
| 9 | MC100LVEL37 |
ON Semiconductor |
Clock Fanout Buffer |
|
| 10 | MC100LVEL38 |
ON Semiconductor |
Clock Generation Chip |
|
| 11 | MC100LVEL38 |
Motorola |
Clock Generation Chip |
|
| 12 | MC100LVEL39 |
Motorola |
2/4 /4/6 Clock Generation Chip |
|