ATI RD/RS600 series systems using AMD CPUs ICS9LPRS464 Key Specifications • • • • CPU outputs cycle-to-cycle jitter <150ps SRC outputs cycle-to-cycle jitter < 125ps ATIG outputs cycle-to-cycle jitter < 125ps +/- 100ppm frequency accuracy on all outputs if REF is tuned to +/-100ppm Output Features • • • • • • • • Integrated Series Resistors on differential.
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• Integrated Series Resistors on differential outputs Greyhound Compatible CPU outputs 2 - 0.7V Low Power differential CPU pairs 6 - 0.7V Low Power differential SRC pairs 2 - 0.7V Low Power differential ATIG pairs 1 - 66 MHz HyperTransport clock 2 - 48MHz USB clocks 3 - 14.318MHz Reference clocks
Features/Benefits:
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• 3 - Programmable Clock Request pins for SRC and ATIG clocks ATIGCLKs are programmable for frequency Spread Spectrum for EMI reduction Outputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy
Pin Configuration
GNDREF .
No. | Partie # | Fabricant | Description | Fiche Technique |
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1 | ICS9LPRS462 |
Integrated Device Technology |
Low Power Clock | |
2 | ICS9LPRS436C |
Integrated Device Technology |
Low Power Clock | |
3 | ICS9LPRS480 |
Integrated Device Technology |
Programmable System Clock | |
4 | ICS9LPRS365 |
ICS |
64-Pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor | |
5 | ICS9LPRS501 |
Renesas |
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR | |
6 | ICS9LPRS501 |
IDT |
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR | |
7 | ICS9LPRS502 |
IDT |
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR | |
8 | ICS9LPRS525 |
Integrated Device Technology |
56-pin CK505 | |
9 | ICS9LPRS525 |
Renesas |
56-pin CK505 | |
10 | ICS9LPRS535 |
Renesas |
VREG | |
11 | ICS9LPRS535 |
Integrated Device Technology |
48-pin CK505 | |
12 | ICS9LPRS545 |
Integrated Circuit Solution |
48-pin CK505 |