ICS9LPRS365 - ICS

ICS9LPRS365 64-Pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus a.

Features

• 2 - CPU differential low power push-pull pairs
• 9 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC clocks Features/Benefits:
• Does not require external pass transistor for voltage regulator
• Integrat.